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Parallel and Distributed Processing Symposium, International

Apr. 26 2004 to Apr. 30 2004

Santa Fe, New Mexico

ISBN: 0-7695-2132-0

Volume:

Table of Contents

Message from the general vice-chairFreely available from IEEE.pp. xliv-xliv
Message from the tutorials chairFreely available from IEEE.pp. xlv-xlv
Message from the industrial track chairFreely available from IEEE.pp. xlvi-xlvi
IPDPS 2004 organizationFreely available from IEEE.pp. xlviii-xlix
IPDPS 2004 technical programFreely available from IEEE.pp. li-liii
Introduction
Workshop IntroductionFreely available from IEEE.pp. 131
Papers
Of Gates and WiresFull-text access may be available. Sign in or learn about subscription options.pp. 132a
Papers
A Parallel Architecture for Secure FPGA Symmetric EncryptionFull-text access may be available. Sign in or learn about subscription options.pp. 132b
Papers
Tuning Reconfigurable Microarchitectures for Power EfficiencyFull-text access may be available. Sign in or learn about subscription options.pp. 133a
Papers
A Reconfigurable Tag Computation Architecture for Terabit Packet SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 133b
Papers
A New Approach for On-line Placement on Reconfigurable DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 134a
Papers
An FPGA Run-Time System for Dynamical On-Demand ReconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 135a
Papers
Models and Reconfiguration Problems for Multi Task Hyperreconfigurable ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 135b
Papers
Runtime Reconfigurable Interfaces — The RTR-IFB ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 136a
Papers
Embedded Software Integration for Coarse-Grain Reconfigurable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 137
Papers
Real-Time Configuration Code Decompression for Dynamic FPGA Self-ReconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 138b
Papers
Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 139a
Papers
Integrated Modeling and Generation of a Reconfigurable Network-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 139b
Papers
Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-Off AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 140a
Papers
Hardware Assisted Two Dimensional Ultra Fast PlacementFull-text access may be available. Sign in or learn about subscription options.pp. 140b
Papers
System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-PlacementFull-text access may be available. Sign in or learn about subscription options.pp. 141a
Papers
Non-Contiguous Linear Placement for Reconfigurable FabricsFull-text access may be available. Sign in or learn about subscription options.pp. 141b
Papers
Impacting Education Using FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 142a
Papers
Developing Large-Scale Field-Programmable Analog ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 142b
Papers
Dynamically Reconfigurable Neuron Architecture for the Implementation of Self-Organizing Learning ArrayFull-text access may be available. Sign in or learn about subscription options.pp. 143a
Papers
Designing a Runtime Reconfigurable Processor for General Purpose ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 143b
Papers
Adaptive Processor: A Model of Stream ProcessingFull-text access may be available. Sign in or learn about subscription options.pp. 144b
Papers
Probabilistic Analysis of Fault Tolerance of FPGA Switch Block ArrayFull-text access may be available. Sign in or learn about subscription options.pp. 145a
Papers
Dynamic Reconfiguration for Management of Radiation-Induced Faults in FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 145b
Papers
Dynamically Configurable Security for SRAM FPGA BitstreamsFull-text access may be available. Sign in or learn about subscription options.pp. 146a
Papers
RECASTER: Synthesis of Fault-Tolerant Embedded Systems Based on Dynamically Reconfigurable FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 146b
Papers
Adaptive System ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 147a
Papers
Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 147b
Papers
Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays — Constraints and MethodologyFull-text access may be available. Sign in or learn about subscription options.pp. 148a
Papers
Overlapping Memory Operations with Circuit Evaluation in Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 148b
Papers
Analysis of High-Performance Floating-Point Arithmetic on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 149b
Papers
Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 150a
Papers
Pipelined Multipliers for Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 150b
Papers
Functional Programming for Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 151a
Papers
A Dynamically-Reconfigurable Image Recognition ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 151b
Papers
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 152
Heterogeneous computing workshopFreely available from IEEE.pp. 99-100
WPDRTS 2004 technical programFreely available from IEEE.pp. 115-116
Reconfigurable architectures workshopFreely available from IEEE.pp. 131-131
Java for parallel and distributed computing workshopFreely available from IEEE.pp. 155-155
Workshop on nature inspired distributed computingFreely available from IEEE.pp. 161-161
APDCM '04 - workshop organizersFreely available from IEEE.pp. 170-170
Workshop on communication architecture for clusters (CAC)Freely available from IEEE.pp. 181-181
Workshop organizersFreely available from IEEE.pp. 188-188
The next generation software programFull-text access may be available. Sign in or learn about subscription options.pp. 3 pp.
Workshop introductionFreely available from IEEE.pp. 215-215
Messages from PDSEC-04 workshop chairsFreely available from IEEE.pp. 227-230
Workshop on massively parallel processingFreely available from IEEE.pp. 257-257
Parallel and distributed systems: testing and debuggingFreely available from IEEE.pp. 263-263
High-performance grid computingFreely available from IEEE.pp. 271-271
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