| Abstract |
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A superscalar microprocessor with a variable number of execution units which are dynamically configured during program execution has been modeled. The runtime behaviour of an executed application is determined using a Trace Cache and the most suitable hardware configuration is loaded dynamically. This paper discusses major design aspects of the ongoing implementation process based on a partial reconfiguration design flow. Thus, some microarchitectural components are put together to form a fixed module while different sets of execution units build up reconfigurable ones. The communication between fixed and reconfigurable modules is assured by Xilinx Bus Macros.
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 Additional Information
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Citation:
Adronis Niyonkuru, Hans Christoph Zeidler,
"Designing a Runtime Reconfigurable Processor for General Purpose Applications,"
ipdps,
p. 143b,
18th International Parallel and Distributed Processing Symposium (IPDPS'04) - Workshop 3,
2004
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