Abstract
This paper deals with one idea to minimize cost of development and test for standard analog IC. At the same time, it gives an industrial approach of a method with the aim of optimizing the time-to-market of a whole family of products. This can be implemented without loosing the product quality and with the opportunity of proceeding to a fast technical improvement of the family performances. The process methodology, based on array of devices on a single wafer is described. Particular emphasis is given to the design and test phases. A short comparison of virtual cycle time between a conventional standard analog IC and a product following the method is illustrated. An estimation of gain on Voltage References family development, in term of test resources, mask levels and time-to-market is given.