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Published Articles >> Table of Contents >> Abstract
Eighth Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT'04)
pp. 120-127
Data Movement Optimization for Software-Controlled On-Chip Memory
Motonobu Fujita, University of Tokyo
Masaaki Kondo, Japan Science and Technology Agency
Hiroshi Nakamura, University of Tokyo
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/INTERA.2004.1299516
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| Abstract |
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In order to overcome performance degradation caused by performance disparity between processor and main memory, there have been proposed several new VLSI architectures which have software controlled on-chip memory in addition to the conventional cache. However, users must specify data allocation/replacement on software controlled on-chip memory and data transfer between the on-chip and off-chip memories to achieve higher performance by utilizing on-chip memory. Because such properties are automatically controlled by hardware in conventional caches, a cost of optimization for a program becomes a matter that should be considered. In this paper, we propose an data movement optimization technique for software-controlled on-chip memory. We evaluated the proposed method using two applications. The results reveal that the proposed technique can drastically reduce memory stall cycles and achieve high performance.
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Citation:
Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura,
"Data Movement Optimization for Software-Controlled On-Chip Memory,"
interact,
pp. 120-127,
Eighth Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT'04),
2004
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