Simulation of a Digital Neuro-Chip for Spiking Neural Networks

Conventional hardware platforms are far from reaching real-time simulation requirements of complex spiking neural networks (SNN). Therefore, we designed an accelerator board with a neuro-processor-chip, called NeuroPipe-Chip. In this paper, we introduce two new concepts on chip-level to speed up the simulation of SNN. The concepts are implemented in the architecture of the NeuroPipe-Chip. We present the hardware structure of the NeuroPipe-Chip, which is modeled on register-transfer-level (RTL) using the hardware description language VHDL. We evaluate the performance of the NeuroPipe-Chip in a system simulation, where the rest of the accelerator board is modeled in behavioral VHDL. For a simple SNN for image segmentation, the NeuroPipe-Chip operating at 100MHz shows an improvement of more than two orders of magnitude compared to an Alpha 500MHz workstation and approaches real-time requirements for SNN in the order of 10 6 neurons. Hence, such an accelerator would allow real-time simulations of complex SNN for image processing. Currently, the implementation of the NeuroPipe-Chip in a 0.35 m digital CMOS technology is investigated.