| Abstract |
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In this paper, we present and discuss the major results of out research activity aimed to the analog VLSI implementation of on-chip learning neural networks. In particular, we present the SLANP (Self Learning Neural Processor) chip results. The SLANP architecture implements on-chip learning Multi Layer Perceptron network. The learning algorithm is based on the Back Propagation but it exhibits increased capabilities due to the local learning rate management. A prototype chip has been designed and fabricated in a CMOS 0.7.... m minimum channel length technology. The experimental results confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favorable with those reported in literature.
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 Additional Information
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Citation:
G.M. Bo, D.D. Caviglia, M. Valle,
"An On-Chip Learning Neural Network,"
ijcnn,
p. 4066,
IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4,
2000
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