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IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4   p. 4062
Programmable Kernel Analog VLSI Convolution Chip for Real Time Vision Processing
T. Serrano-Gotarredona, Instituto de Microelectrónica de Sevilla
B. Linares-Barranco, Instituto de Microelectrónica de Sevilla
A.G. Andreou, Instituto de Microelectrónica de Sevilla

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IJCNN.2000.860750
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Abstract
Human beings have the capability of recognizing objects, figures, and shapes even if they appear embedded within noise, are partially occluded or look distorted. To achieve this, the human vision processing system is structured into a number of massively interconnected neural layers with feedforward and feedback connections among them. Neurons communicate by means of electrical streams of pulses. Each neuron broadcasts its output to a large number of other neurons, which can be inside the same or at different layers, and the way this is done is through physical connections called synapses [1]. One big problem encountered by engineers when it comes to implement bio-inspired (vision) processing systems is to overcome the massive interconnections. The Address Even Representation (AER) [2]-[5] approach is a possible solution. Fig. 1 shows a schematic figure outlining the essence behind AER. Suppose we have an “emitter” chip containing a large number of neurons or cells D1, D2, D3, ... whose activity changes in time with a “relatively slow” time constant. For example, if Chip 1 is a retina chip and each neuron's activity represents the illumination sensed by a pixel, the time constant with which this activity changes can be equivalent to Frame-Rate (i.e., 25-30 changes per second or a time constant of about 30-40ms) 1. The purpose of an AER based communication scheme is to be able to reproduce the time evolution of each neuron's activity inside a second or “receiver” chip, using a fast digital bus with a small number of pins. In the “emitter” chip the activity of each pixel has to be transformed into a pulse stream signal such that pulse width is minimum and the spacing between pulses is reasonably high to time multiplex the activity of a relatively large number of neurons. Every time a neuron produces a pulse, its address or code should be written on the bus. For the case more than one pulses are produced simultaneously by several neurons, a classical arbitration tree can be introduced [2]-[4], or one based in Winner-Takes-All (WTA) row-wise competitions [6], or simply by making no neuron accessing the bus in case of a “collision” [7].Whatever method is used the result will be the presence of a sequence of addresses or codes on the digital bus that one or more receiver chips can read. Each receiver chip must contain a decoding circuitry so that a pulse reaches the neuron (or neurons) specified by the address read on the bus. If each neuron integrates the sequence of pulses properly, the original activity of the neurons in the emitter chip will be reproduced. AER allows easily adding more complicated processing. For example, input images can be translated or rotated by remapping the addresses while they travel from one chip to the next. By properly programming an EEPROM as a look-up table, any address remapping can be implemented, by simply inserting the EEPROM between the two chips. Furthermore, many EEPROMs can be connected in parallel each performing, for example, a rotation at a specific angle, and each delivering the remapped addresses to a set of specialized processing chips. In the architecture proposed in this paper, we implement a synaptically weighted projection field for each address read on the bus. This can be done by either having a hard-wired kernel in the filtering chip [8], or by implementing a programmable one, as proposed in this paper.
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Citation:  T. Serrano-Gotarredona, B. Linares-Barranco, A.G. Andreou, "Programmable Kernel Analog VLSI Convolution Chip for Real Time Vision Processing," ijcnn, p. 4062,  IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4,  2000