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2004 IEEE International Conference on Computer Design (ICCD'04)   pp. 505-508
Coping with The Variability of Combinational Logic Delays
J. Cortadella, Univ. Politècnica Catalunya, Barcelona, Spain
A. Kondratyev, Cadence Berkeley Labs, Berkeley, CA
L. Lavagno, Politenico di Torino, Italy
C. Sotiriou, ICS-FORTH, Crete, Greece

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2004.1347969
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Abstract
This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead and reasonable area and power overhead. We discuss various scenarios in which completion detection can be used to measure the delay of a synchronous circuit at fabrication time or at run time, and of an asynchronous circuit at run time. We conclude by showing, on a large set of benchmarks, the effectiveness of the proposed technique.
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Citation:  J. Cortadella, A. Kondratyev, L. Lavagno, C. Sotiriou, "Coping with The Variability of Combinational Logic Delays," iccd, pp. 505-508,  2004 IEEE International Conference on Computer Design (ICCD'04),  2004