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2004 IEEE International Conference on Computer Design (ICCD'04)   pp. 42-47
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure
Jung-Wook Park, CS, Yonsei University, Korea
Gi-Ho Park, Samsung Electronics Co., LTD. Giheung, Korea
Sung-Bae Park, Samsung Electronics Co., LTD. Giheung, Korea
Shin-Dug Kim, CS, Yonsei University, Korea

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2004.1347896
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Abstract
This paper proposes a power-aware cache block allocation algorithm for the way-selective set-associative cache on embedded systems to reduce energy consumption without additional delay or performance degradation. For this goal, way selection logic and specialized replacement policy are designed to enable only one way of set-associative cache as in the direct-mapped cache. Overall cache access time becomes almost the same as that of conventional set associative cache with accessing additional way selection logic. Because data array can be accessed without waiting for tag comparison, multiplexer delay can be removed totally. The simulation result shows that the proposed architecture can reduce a per access power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.
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Citation:  Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim, "Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure," iccd, pp. 42-47,  2004 IEEE International Conference on Computer Design (ICCD'04),  2004