An Efficient Twin-Precision Multiplier

Magnus Sj?lander; Henrik Eriksson; Per Larsson-Edefors

doi:10.1109/ICCD.2004.1347894

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.

An Efficient Twin-Precision Multiplier

Year: 2004, Pages: 30-33

DOI Bookmark: 10.1109/ICCD.2004.1347894

Authors

Magnus Sj?lander, Chalmers University of Technology, Sweden
Henrik Eriksson, Chalmers University of Technology, Sweden
Per Larsson-Edefors, Chalmers University of Technology, Sweden

Abstract

We present a twin-precision multiplier that in normal operation mode efficiently performs N-b multiplications. For applications where the demand on precision is relaxed, the multiplier can perform N/2-b multiplications while expending only a fraction of the energy of a conventional N-b multiplier. For applications with high demands on throughput, the multiplier is capable of performing two independent N/2-b multiplications in parallel. A comparison between two signed 16-b multipliers, where both perform single 8-b multiplications, shows that the twin-precision multiplier has 72% lower power dissipation and 15% higher speed than the conventional one, while only requiring 8% more transistors.

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An Efficient Twin-Precision Multiplier

Authors

Abstract

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