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2002 IEEE International Conference on Computer Design (ICCD'02)   p. 174
Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study
Hongbo Yang, University of Delaware
R. Govindarajan, Indian Institute of Science at Bangalore
Guang R. Gao, University of Delaware
Kevin B. Theobald, University of Delaware

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.1106766
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Abstract
The drastic increase in power consumption by modern processors emphasizes the need for power-performance trade-offs in architecture design space exploration and compiler optimizations. This paper reports a quantitative study on the power-performance trade-offs in software pipelined schedules for an Itanium-like EPIC architecture with dual-speed pipelines, in which functional units are partitioned into fast ones and slow ones. We have developed an integer linear programming formulation to capture the power-performance tradeoffs for software pipelined loops. The proposed integer linear programming formulation and its solution method have been implemented and tested on a set of SPEC2000 benchmarks. The results are compared with an Itanium-like architecture(baseline) in which there are four functional units (FUs) and all of them are fast units. Our quantitative study reveals that by introducing a few slow FUs in place of fast FUs in the baseline architecture, the total energy consumed by FUs can be considerably reduced. When 2 out of 4 FUs are set as slow, the total energy consumed by FUs is reduced by up to 31.1% (with an average reduction of 25.2%) compared with the baseline configuration, while the performance degradation caused by using slow FUs is small. If performance demand is less critical, then energy reduction of up to 40.3% compared with the baseline configuration can be achieved.
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Citation:  Hongbo Yang, R. Govindarajan, Guang R. Gao, Kevin B. Theobald, "Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study," iccd, p. 174,  2002 IEEE International Conference on Computer Design (ICCD'02),  2002