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Published Articles >> Table of Contents >> Abstract
2002 IEEE International Conference on Computer Design (ICCD'02)
p. 98
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture
Sumio Morioka, IBM Japan Ltd.
Akashi Satoh, IBM Japan Ltd.
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.1106754
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In this paper, we present a high-speed AES IP-core, which runs at 780 MHz on a 0.13µm CMOS standard cell library, and which achieves 10 Gbps throughput in all encryption modes, including CBC mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining techniques cannot be applied. To reduce the propagation delays of the S-Box, the most critical function block, we developed a special circuit architecture that we call twisted-BDD, where the fanout of signals is distributed in the S-Box circuit. Our S-Box is 1.5 to 2 times faster than the conventional S-Box implementations. The T-Box algorithm, which merges the S-Box and another primitive function (MixColumns) into a single function, is also used for an additional speedup.
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Citation:
Sumio Morioka, Akashi Satoh,
"A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture,"
iccd,
p. 98,
2002 IEEE International Conference on Computer Design (ICCD'02),
2002
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