Abstract
We developed a methodology and tools for synthesizing monotonic networks, which consist of alternating low-skew and high-skew logic gates. By taking advantage of their reduced input capacitance, lower switching thresholds, and efficient implementation for wide complex gates, monotonic circuits can obtain greater performance compared to static CMOS. Our results show standard domino, dynamic-static domio, monotonic static CMOS, and zipper CMOS to have average speed improvements of 1.57, 1.66, 1.67, and 1.47 times over static CMOS, respectively.