Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)
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Abstract

This paper presents the low power architecture of CalmRISC, a low power 8-bit microcontroller consuming only 0.1mW per MIPS at 3.0V, and its efficient coprocessor interface. The architectural consideration of CalmRISC for low power consumption is presented. Some low power circuit design schemes as well as an efficient coprocessor interface scheme in CalmRISC are proposed and discussed.
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