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10th International Symposium on High Performance Computer Architecture (HPCA'04)   p. 2
Exploiting Prediction to Reduce Power on Buses
Victor Wen, University of California at Berkeley
Mark Whitney, University of California at Berkeley
Yatish Patel, University of California at Berkeley
John D. Kubiatowicz, University of California at Berkeley

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HPCA.2004.10025
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Abstract
We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified SimpleScalar simulator and SPEC benchmarks. We show an average of 35% savings in transitions on internal buses. To quantify actual power savings, we design a dictionary based encoder/decoder circuit in a 0.13µm process, extract it as a netlist, and simulate its behavior under SPICE. Utilizing a realistic wire model with repeaters, we show that we can break even at median wire length scales of less than 11.5mm at 0.13µ and project a break-even point of 2.7mm for a larger design at 0.07µ.
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Citation:  Victor Wen, Mark Whitney, Yatish Patel, John D. Kubiatowicz, "Exploiting Prediction to Reduce Power on Buses," hpca, p. 2,  10th International Symposium on High Performance Computer Architecture (HPCA'04),  2004