A Design for testability Method Using RTL Partitioning

We will present a Design For Testability (DFT) method on Register Transfer Level (RTL). In our method, RTL circuits are partitioned into some testable blocks, and each of the blocks is isolated by using primary pins so that automatic test pattern generation (ATPG) can be applied for each of the blocks. In this paper, we will discuss the definition of testable circuits from the point of view of difficulty of ATPG for sequential circuits. We will present a DFT method without scan design on RTL using partitioning and isolation. The experimental results for some RTL circuits designed with Bchart show that our method reduces the number of test patterns from a seventeenth to an eightieth and 10 to 30% of area overhead for test circuit in comparison with full scan design method.