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7th Great Lakes Symposium on VLSI   p. 182
A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines
Eric Gayles, The Pennsylvania State University
Kevin Acken, The Pennsylvania State University
Robert Owens, The Pennsylvania State University
Mary Jane Irwin, The Pennsylvania State University
Kevin Acken, Penn State University

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580539
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Abstract
This paper presents a CMOS circuit methodology for designing pipeline stages which are both faster than comparable domino based stages and that also have increased functional capability. The basic gates offer considerably faster switching speeds than domino, while also eliminating the feedback and buffering circuitry required by domino gates for reliable operation. In addition to faster gates, the dual-rail nature of the proposed circuit technique provides greater logic functionality per gate. This results in a reduction of the number of gate delays required for implementing complex functions of high fan-in. Several benchmark circuits were simulated in a 0.5 micron, 3.3 V CMOS process. The results show that the proposed circuit technique provides significant speed improvement over domino.
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Citation:  Eric Gayles, Kevin Acken, Robert Owens, Mary Jane Irwin, Kevin Acken, "A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines," glsvlsi, p. 182,  7th Great Lakes Symposium on VLSI,  1997