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Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)   p. 106
Partitioning transition relations efficiently and automatically
Z. Zhou, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
X. Song, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
F. Corella, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
E. Cerny, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
M. Langevin, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516034
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Abstract
Multiway Decision Graphs (MDGs) have been recently proposed as an efficient representation of Extended Finite State Machines (EFSMs), suitable for automatic hardware verification of Register Transfer Level (RTL) designs. We report here on the results of our research into automatic partitioning of state transition relations described using MDGs. The objective is to achieve the maximum possible performance during an abstract implicit state enumeration procedure that is at the basis of our automatic verification method.
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Index Terms- logic partitioning; logic CAD; graph theory; state estimation; finite state machines; automatic partitioning; state transition relations; multiway decision graphs; abstract implicit state enumeration procedure; automatic verification method; extended finite state machines; register transfer level designs Citation:  Z. Zhou, X. Song, F. Corella, E. Cerny, M. Langevin, "Partitioning transition relations efficiently and automatically," glsvlsi, p. 106,  Fifth Great Lakes Symposium on VLSI (GLSVLSI'95),  1995