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Published Articles >> Table of Contents >> Abstract
Fourth International ACM Symposium on Field-Programmable Gate Arrays (FPGA'96)
pp. 137-143
RASP: A General Logic Synthesis System for SRAM-Based FPGAs
Jason Cong, University of California, Los Angeles
John Peck, University of California, Los Angeles
Yuzheng Ding, AT&T Bell Laboratories, Murray Hill, NJ
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1996.14
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In this paper, we present a general synthesis system for SRAM-based FPGAs named RASP. RASP consists of a core with a set of synthesis and optimization algorithms for technology independent logic synthesis and technology mapping for generating generic look-up tables (LUTs), together with a set of architecture-specific technology mapping routines to map the generic LUT network to programmable logic blocks (PLBs) for various SRAM-based FPGA architectures. Via a set of design representation converter routines, these architecture-independent and dependent synthesis algorithms are easily linked, and the entire system is seamlessly integrated into the design flow of commercial FPGA design systems. As a result, RASP can produce highly optimized designs for various SRAM-based FPGA architectures, and can be quickly adapted for new SRAM-based FPGA architectures. We compare RASP performance with that of several commercial synthesis systems on the MCNC logic synthesis benchmarks and a video compressor/decompressor. For almost all cases, RASP produces mapping solutions with significantly smaller critical path delay after place and route than current commercial synthesis systems.
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 Additional Information
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Citation:
Jason Cong, John Peck, Yuzheng Ding,
"RASP: A General Logic Synthesis System for SRAM-Based FPGAs,"
fpga,
pp. 137-143,
Fourth International ACM Symposium on Field-Programmable Gate Arrays (FPGA'96),
1996
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