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12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04)   pp. 328-329
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
Noriaki Suzuki, Keio University, Japan
Shunsuke Kurotaki, Keio University, Japan
Masayasu Suzuki, Keio University, Japan
Naoto Kaneko, Keio University, Japan
Yutaka Yamada, Keio University, Japan
Katsuaki Deguchi, Keio University, Japan
Yohei Hasegawa, Keio University, Japan
Hideharu Amano, Keio University, Japan
Kenichiro Anjo, NEC Electronics, Japan
Masato Motomura, NEC Electronics, Japan
Kazutoshi Wakabayashi, NEC System Devices Research Lab., Japan
Takeo Toi, NEC System Devices Research Lab., Japan
Toru Awashima, NEC System Devices Research Lab., Japan

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.42
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Abstract
Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the first prototype chip, and evaluation results are presented. By computing parallelly using the Processing Elements(PEs) and distributed memory modules, DRP-1 out-performed Pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance.
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Citation:  Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima, "Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor," fccm, pp. 328-329,  12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04),  2004