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Published Articles >> Table of Contents >> Abstract
12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04)
pp. 324-325
An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic
Daniel J. Allred, Georgia Institute of Technology, Atlanta, GA
Walter Huang, Georgia Institute of Technology, Atlanta, GA
Venkatesh Krishnan, Georgia Institute of Technology, Atlanta, GA
Heejong Yoo, Georgia Institute of Technology, Atlanta, GA
David V. Anderson, Georgia Institute of Technology, Atlanta, GA
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.15
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| Abstract |
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In this paper, an FIR adaptive filter implementation using a multiplier-free architecture is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT. The system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed LMS adaptive filter can be realized employing the proposed architecture.
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 Additional Information
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Citation:
Daniel J. Allred, Walter Huang, Venkatesh Krishnan, Heejong Yoo, David V. Anderson,
"An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic,"
fccm,
pp. 324-325,
12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04),
2004
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