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12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04)   pp. 115-124
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
Raj Krishnamurthy, IBM Research Zurich Labs, Switzerland
Sudhakar Yalamanchili, Georgia Institute of Technology, Atlanta, GA
Karsten Schwan, Georgia Institute of Technology, Atlanta, GA
Richard West, Georgia Institute of Technology, Atlanta, GA

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.52
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Abstract
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a unified hardware architecture for realizing a range of wire-speed packet scheduling disciplines for output link scheduling. This paper presents opportunities to exploit parallelism, design issues, tradeoffs and evaluation of the FPGA hardware architecture for use in switch network interfaces. The architecture uses processor resources for queueing & data movement and FPGA hardware resources for accelerating decisions and priority updates. The hardware architecture stores state in Register base blocks, stream service attributes are compared using single-cycle decision blocks arranged in a novel single-stage recirculating network. The architecture provides effective mechanisms to trade hardware complexity for lower execution-time in a predictable manner. The hardware realized in a Virtex-I and Virtex-II FPGA can meet the packet-time requirements of 10Gbps links for 256 stream queues with window-constrained scheduling disciplines. The hardware can schedule 1536 stream queues with priority-class/fair-queueing scheduling disciplines using 16 service-classes to meet 10Gbps packet-times.
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Citation:  Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West, "ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers," fccm, pp. 115-124,  12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04),  2004