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Published Articles >> Table of Contents >> Abstract
11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
p. 121
Asynchronous PipeRench: Architecture and Performance Estimations
Hiroto Kagotani, Okayama University
Herman Schmit, Carnegie Mellon University
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.2003.1227248
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| Abstract |
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PipeRench is a configurable architecture that has the unique ability to virtualize an application using dynamic reconfiguration. This paper investigates the potential benefits and costs of implementing this architecture using an asynchronous methodology. Since clock distribution and gating are relatively easy in the synchronous PipeRench, we focus on the benefit due to decreased timing pessimism in an asynchronous implementation. Two architectures for fully asynchronous implementation are considered. PE-based asynchronous implementation yields approximately 80% improvement in performance per stripe. This implementation, however, requires significant increases in configuration storage and wire count. A few particular features of the architecture, such as the crossbar interconnect structure within the stripe, are primarily responsible for this growth in configuration bits and wires. These features, however, are the primary aspects of the PipeRench architecture that make it a good compilation target.
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 Additional Information
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Citation:
Hiroto Kagotani, Herman Schmit,
"Asynchronous PipeRench: Architecture and Performance Estimations,"
fccm,
p. 121,
11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines,
2003
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