Accelerating Bit Error Rate Testing Using a System Level Design Tool

System level design tools for creating DSP designs reduce the amount of time needed to create a DSP design, in part by eliminating the need for verification between system model and hardware implementation. The design is developed within a high level modeling environment. This description is compiled into a hardware description language, and synthesized by traditional FPGA tools. The use of system level tools can eliminate the need for an extensive hardware knowledge. This paper demonstrates how such tools can be used to build a Bit Error Rate (BER) tester, and how hardware co-simulation of the entire system provided a 10,000x speed-up over a pure software simulation.