|
Published Articles >> Table of Contents >> Abstract
2000 IEEE Symposium on Field-Programmable Custom Computing Machines
p. 113
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm)
Cameron Patterson, Xilinx, Inc.
Full Article Text:
  
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.2000.903398
Send link to a friend
| Abstract |
|
A JBits implementation of the Data Encryption Standard (DES) algorithm in a Virtex FPGA is described. The Virtex architecture efficiently implements the DES primitive operations, and permits a high degree of pipelining. JBits provides a Java-base d Application Programming Interface (API) for the runtime creation and modification of the configuration bitstream. This allows dynamic circuit specialization based on a specific key and mode (encrypt or decrypt). The key schedule is computed entirely in software, and is part of the bitstream. As a result, all cryptographic key input and subkey generation logic are removed from the fully unrolled datapath. When combined with a speed efficient layout, the result is a throughput of over 10 Gigabits per second. This exceeds the performance of a recently announced DES ASIC.
|
 Additional Information
|
Citation:
Cameron Patterson,
"High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm),"
fccm,
p. 113,
2000 IEEE Symposium on Field-Programmable Custom Computing Machines,
2000
|
|
