| Abstract |
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In recent years, interest in the area of custom computing machines (CCMs) has been on a steady increase. Much of the activity surrounding CCMs has centered around Field-Programmable Gate Array (FPGA) technology and rapid prototyping applications. For supporting applications, FPGAs are reconfigured to allow pieces of the application to be mapped on it temporally. The performance of the FPGA when used as virtual hardware engine depends on its reconfiguration granularity. We study the striped FPGA, and propose a hybrid mechanism to process a large amount of data using a combination of data and configuration caching. We also present our analysis, quantifying total execution time and I/O overhead presented by the scheme to determine its applicability domain.
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 Additional Information
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Index Terms- Striped FPGAs, data caching, configuration caching
Citation:
Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi,
"Hybrid Data/Configuration Caching for Striped FPGAs,"
fccm,
p. 294,
Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines,
1999
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