| Abstract |
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We propose a smart compilation chain in which the compiler is no longer limited by a pre-defined instruction set, but can generate application-specific custom instructions and synthesize them in Field-Programmable Logic. We also present a RISC micro-architecture enhanced by a CPLD-based Reconfigurable Functional Unit (RFU) which supports our compiler approach. The main difference between our smart compiler and similar methods is the ability to encode multiple custom instructions in a singleRFU configuration, cross-minimizing the logic among them. The objective is to reduce (or eliminate) the reconfiguration overhead and optimize the utilization of resources. The CPLD core that implements the RFU is based on the Philips XPLA2 architecture.We discuss the advantages of using the XPLA2 instead of conventional FPGAs. Application examples are also presented, which show that our RFU-extended CPU can achieve speed-ups of more than 40% for encryption algorithms, when compared to the standard CPU core alone.
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 Additional Information
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Index Terms- computer-architecture, reconfigurable-computing, CPLD, programmable-logic, custom-instructions, hardware-acceleration, XPLA, compilers, static-analysis, compiler-optimizations
Citation:
Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge,
"ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator,"
fccm,
p. 92,
Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines,
1999
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