Digit-Serial DSP Library for Optimized FPGA Configuration

IEEE Symposium on FPGAs for Custom Computing Machines p. 322
Digit-Serial DSP Library for Optimized FPGA Configuration
Hanho Lee, University of Minnesota
Gerald E. Sobelman, University of Minnesota

Full Article Text:

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1998.707936
Send link to a friend

Abstract
This paper gives the digit-serial DSP libraries used to implement the digit-serial DSP architecture for field programmable gate arrays (FPGAs) and compares schematic-based FPGA design with design based on logic synthesis for digit-serial DSP libraries. It describes the design of digit-serial addition/subtraction, multiplication and delay elements and indicates also how digit-serial FIR filter can be implemented. The FPGA device utilization and critical path delay of digit-serial DSP libraries are calculated and described.
Back to Top Additional Information
Citation: Hanho Lee, Gerald E. Sobelman, "Digit-Serial DSP Library for Optimized FPGA Configuration," fccm, p. 322, IEEE Symposium on FPGAs for Custom Computing Machines, 1998

	Advanced Search
CS Search Google Search