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IEEE Symposium on FPGAs for Custom Computing Machines   p. 138
Configuration Compression for the Xilinx XC6200 FPGA
Scott Hauck, Northwestern University
Zhiyuan Li, Northwestern University
Eric Schwabe, Northwestern University

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1998.707891
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Abstract
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting new paradigm. In this paper we explore one technique for reducing this overhead: the compression of configuration datastreams. We develop an algorithm, targeted to the decompression hardware imbedded in the Xilinx XC6200 series FPGA architecture, that can radically reduce the amount of data needed to transfer during reconfiguration. This results in an overall reduction of almost 4 in total bandwidth required for reconfiguration.
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Citation:  Scott Hauck, Zhiyuan Li, Eric Schwabe, "Configuration Compression for the Xilinx XC6200 FPGA," fccm, p. 138,  IEEE Symposium on FPGAs for Custom Computing Machines,  1998