Abstract
This paper presents a new method for specifying chip-level interfaces, named the unified modeling graph(UMG). The UMG firstly combines the features of both the finite state machine(FSM) and the signal transition graph(STG) to achieve a unified representation of various interfaces. It is more user-friendly than the conventional methods and more importantly, the method specifies scheduling constraints of interface behavior in a well-defined compact form. With such features, it is useful for describing and synthesizing chip-level interfaces , which is shown by several illustrative examples.