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25th Euromicro Conference (EUROMICRO '99)-Volume 1   p. 1126
The X-MatchLITE FPGA-Based Data Compressor
Jose Luis Nunez, Loughborough University
Claudia Feregrino, Loughborough University
Simon Jones, Loughborough University
Stephen Bateman, GateField Corporation

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EURMIC.1999.794458
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Abstract
This paper introduces a hardware amenable algorithm for lossless data compression and a highly integrable architecture which enables Gbit/s compression using contemporary ASIC technology. An FPGA prototype of the architecture is presented. A comparison between this prototype and the full version of the system is made together with the details of the engineering decisions needed to successfully realize an ASIC compressor in FPGA technology.
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Citation:  Jose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman, "The X-MatchLITE FPGA-Based Data Compressor," euromicro, p. 1126,  25th Euromicro Conference (EUROMICRO '99)-Volume 1,  1999