Abstract
Little has been published on self-synchronized circuits, a design style that is very useful in practical controller design; for instance in interfaces and controls of self-timed realizations. There are few researches on VLSI realization of low power (pass transistor-based) and other asynchronous self-synchronized sequential circuits [16, 10, 11, 1, 2]. The goal is to achieve fast circuits, with low power consumption, for deep sub-micron technologies. The U.C. Berkeley project [1] proposes synchronization and communication between a number of processors that operate at varying clock rates and voltage levels. They propose the use of a "data-driven asynchronous approach at the protocol level". This is combined with an "locally synchronous island" approach at the circuit level that allows for the reconfigurable interconnect network to operate in a self-timed mode at low voltage swing. "Processor modules can be operating in either synchronous or self-timed mode at arbitrary voltage levels. The combination of a data-driven communication protocol and the locally synchronous islands eliminates the occurrence of synchronization failures" [1]. However, no specialized set of EDA tools or PLDs are now available that can be used for fast prototyping of such systems and FPGA components in them. This paper proposes a new design style for self-synchronized state machines, demonstrates their usefulness by speed analysis, compares variants using a simple example, and proposes new types of EPLD/FPGA chips to aid in the board-level design of self-synchronized circuits.