Published Articles >> Table of Contents
2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
| Introduction |
Preface (PDF)
p. viii
 
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Conference Organizers (PDF)
p. ix
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Program Committee (PDF)
p. x
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Group Posters (PDF)
p. xi
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| Invited Talks |
We Need Assurance (PDF)
Brian Snow, National Security Agency
p. 3
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The Failure of a Small Satellite and the Loss of a Space Science Mission (PDF)
Rich Katz, NASA
p. 4
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Evolvable Hardware for Industrial Applications
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Dependable Reconfigurable Computing Design Diversity and Self Repair (PDF)
Subhasish Mitra, Intel Corporation and Stanford University
Edward J. McCluskey, Stanford University
p. 5
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Life, the Universe, and Everything: 4.5 Billion Years of Evolvable Hardware (PDF)
John D. Rummel, NASA Headquarters
p. 6
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Physical Support for Evolution in Reconfigurable Devices (PDF)
Peter Athanas, Virginia Polytechnic Institute and State University
p. 7
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Getting Most Out of Evolutionary Approaches (Abstract)
Xin Yao, University of Birmingham
Yong Liu, University of Aizu
p. 8
 
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| 1. Evolution of Digital Systems |
Evolvable Hardware for the Generation of Sequential Filter Circuits (Abstract)
Robert Thomson, University of Edinburgh
Tughrul Arslan, University of Edinburgh
p. 17
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The Robustness of Small Developped SBlock Circuits Using Different Clocking Schemes (Abstract)
Piet van Remortel, Vrije Universiteit Brussel
Tom Lenaerts, Vrije Universiteit Brussel
Bernard Manderick, Vrije Universiteit Brussel
p. 26
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Evolving Robust Digital Designs (Abstract)
Morten Hartmann, Norwegian University of Science and Technology
Pauline Haddow, Norwegian University of Science and Technology
Frode Eskelund, Norwegian University of Science and Technology
p. 36
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Self-Assembling Circuits with Autonomous Fault Handling (Abstract)
Nicholas J. Macias, Cell Matrix Corporation
Lisa J. K. Durbeck, Cell Matrix Corporation
p. 46
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On Two New Trends in Evolvable Hardware: Employment of HDL-Based Structuring, and Design of Multi-Functional Circuits (Abstract)
Adrian Stoica, California Institute of Technology
Didier Keymeulen, California Institute of Technology
Ricardo S. Zebulum, California Institute of Technology
M. I. Ferguson, California Institute of Technology
p. 56
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Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic (Abstract)
Channakeshav, Rensselaer Polytechnic Institute
K. Zhou, Rensselaer Polytechnic Institute
R. Kraft, Rensselaer Polytechnic Institute
J. F. McDonald, Rensselaer Polytechnic Institute
p. 60
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Evolutionary Technique to Elementary Coding of the Internal States of the State Machine (PDF)
Igor V. Vasiltsov, Ternopil Academy of National Economy
p. 63
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| 2. Evolution of Analog Systems |
Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System (Abstract)
Adrian Stoica, California Institute of Technology
Ricardo S. Zebulum, California Institute of Technology
M. I. Ferguson, California Institute of Technology
Didier Keymeulen, California Institute of Technology
Vu Duong, California Institute of Technology
p. 67
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Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip (Abstract)
Jorg Langeheine, Heidelberg University
Karlheinz Meier, Heidelberg University
Johannes Schemmel, Heidelberg University
p. 75
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Automated Design of Analog Circuits Using Cell-Based Structure (Abstract)
Hajime Shibata, Analog Devices K.K.
Soji Mori, Tokyo Institute of Technology
Nobuo Fujii, Tokyo Institute of Technology
p. 85
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Application of the Univariate Marginal Distribution Algorithm to Analog Circuit Design (Abstract)
Lyudmilla Zinchenko, Taganrog State University of Radioengineering
Heinz Muhlenbein, Theoretical Foundation GMD Lab
Victor Kureichik, Taganrog State University of Radioengineering
Thilo Mahnig, Theoretical Foundation GMD Lab
p. 93
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Chromosome Representation through Adjacency Matrix in Evolutionary Circuits Synthesis (Abstract)
A. Mesquita, Federal University of Rio de Janeiro
Fabio A. Salazar, Federal University of Rio de Janeiro
P. Paulo Canazio, Federal University of Rio de Janeiro
p. 102
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| 3. Evolution of Controllers |
Automatic Synthesis Using Genetic Programming of an Improved General-Purpose Controller for Industrially Representative Plants (Abstract)
Martin A. Keane, Econometrics Inc.
John R. Koza, Stanford University
Matthew J. Streeter, Genetic Programming Inc.
p. 113
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Towards Evolvable Analog Fuzzy Logic Controllers (Abstract)
Jose Franco Machado do Amaral, Rio de Janeiro State University
Jorge Luis Machado do Amaral, Rio de Janeiro State University
Cristina C. Santini, Catholic University of Rio de Janeiro
Ricardo Tanscheit, Catholic University of Rio de Janeiro
Marley Maria R. Vellasco, Catholic University of Rio de Janeiro
Marco Aurelio C. Pacheco, Catholic University of Rio de Janeiro
p. 123
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How to Evolve Safe Control Strategies (PDF)
G. W. Greenwood, Portland State University
X. Song, Portland State University
p. 129
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| 4. Real World Applications |
An EHW Architecture for Real-Time GPS Attitude Determination Based on Parallel Genetic Algorithm (Abstract)
Jiangning Xu, University of Edinburgh
T. Arslan, University of Edinburgh
p. 133
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The Implementation of an Evolvable Hardware System for Real Time Image Registration on a System-on-Chip Platform (Abstract)
J. R. Evans, University of Edinburgh
T. Arslan, University of Edinburgh
p. 142
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Optimizing Signal Strength In-Situ Using an Evolvable Antenna System (Abstract)
Derek S. Linden, Linden Innovation Research
p. 147
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Evolving Optimal Parameters for Swarm Control (PDF)
Jennifer Golbeck, University of Maryland at College Park
p. 152
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Coevolution of Form and Function in the Design of Micro Air Vehicles (Abstract)
Magdalena D. Bugajska, Naval Research Laboratory
Alan C. Schultz, Naval Research Laboratory
p. 154
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| 5. New Avenues for Evolvable Hardware |
Evolution in materio: Looking Beyond the Silicon Box (Abstract)
Julian F. Miller, University of Birmingham
Keith Downing, Norwegian University of Science and Technology
p. 167
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Evolving Quantum Circuits Using Genetic Algorithm (Abstract)
Martin Lukac, Portland State University
Marek Perkowski, Portland State University
p. 177
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Evolution of Quantum Algorithms for Computer of Reversible Operators (PDF)
Alvin J. Surkan, University of Nebraska at Lincoln
Amiran Khuskivadze, University of Nebraska at Lincoln
p. 186
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| 6. Cellular Automata |
High-Performance Cellular Automata Random Number Generators for Embedded Probabilistic Computing Systems (Abstract)
Barry Shackleford, Hewlett-Packard Laboratories
Motoo Tanaka, Hewlett-Packard Laboratories
Richard J. Carter, Hewlett-Packard Laboratories
Greg Snider, Hewlett-Packard Laboratories
p. 191
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Self-Reproduction in Asynchronous Cellular Automata (Abstract)
Chrystopher L. Nehaniv, University of Hertfordshire
p. 201
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Evolving Cellular Automata to Model Fluid Flow in Porous Media (Abstract)
Tina Yu, ChevronTexaco Information Technology Company
Seong Lee, ChevronTexaco Exploration & Production Technology Company
p. 210
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| 7. Embryonics and Bio-Inspired Architectures |
The BioWall: An Electronic Tissue for Prototyping Bio-Inspired Systems (Abstract)
Gianluca Tempesti, Swiss Federal Institute of Technology in Lausanne
Daniel Mange, Swiss Federal Institute of Technology in Lausanne
Andre Stauffer, Swiss Federal Institute of Technology in Lausanne
Christof Teuscher, Swiss Federal Institute of Technology in Lausanne
p. 221
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Implementing Asynchronous Embryonic Circuits using AARDVArc (Abstract)
Alexander H. Jackson, University of York
Andrew M. Tyrrell, University of York
p. 231
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Towards Development in Evolvable Hardware (Abstract)
Timothy G. W. Gordon, University College London
Peter J. Bentley, University College London
p. 241
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Circuit Morphologies and Ontogenies (Abstract)
R. Timothy Edwards, Johns Hopkins University
p. 251
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An Immunochip Architecture and Its Emulation (Abstract)
Alexander Tarakanov, Russian Academy of Sciences
Dipankar Dasgupta, University of Memphis
p. 261
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Towards an Artificial Neural Network Framework (Abstract)
Felix Schurmann, Heidelberg University
Steffen Hohmann, Heidelberg University
Johannes Schemmel, Heidelberg University
Karlheinz Meier, Heidelberg University
p. 266
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Reversible Evolvable Networks: A Reversible Evolvable Boolean Network Architecture and Methodology to Overcome the Heat Generation Problem in Molecular Scale Brain Building (PDF)
Hugo de GARIS, Utah State University
Jonathan DINERSTEIN, Utah State University
Ravichandra SRIRAM, Utah State University
p. 274
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"TiPo" — A "Timed Pointer" Neural Net Model with Superior Evolvabilities for Implementation in a Second-Generation Brain-Building Machine BM2 (Abstract)
Jonathan Dinerstein, Sorenson Media, Inc.
Hugo de Garis, Utah State University
p. 276
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| Author Index |
Author Index (PDF)
p. 279
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