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1995 European Design and Test Conference (ED&TC '95)   p. 372
Built-in intermediate voltage testing for CMOS circuits
Jing-Jou Tang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Kuen-Jong Lee, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Bin-Da Liu, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EDTC.1995.470369
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Abstract
In this paper, we propose a new testing technique called built-in intermediate voltage testing for CMOS circuits. This technique provides a high quality test which cannot be achieved by conventional functional testing. Three novel circuit designs that can detect faults resulting in intermediate voltage values are presented. These designs can also be used to detect slow transition faults and the metastability of flip-flops. The detection speed, area overhead, circuit complexity, and the performance impact on the circuits under test are analyzed. The results validate the feasibility of these designs in CMOS testing.
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Index Terms- built-in self test; CMOS logic circuits; integrated circuit testing; circuit stability; flip-flops; fault diagnosis; logic testing; sequential circuits; design for testability; built-in intermediate voltage testing; CMOS circuits; intermediate voltage values; slow transition faults; metastability; flip-flops; detection speed; area overhead; circuit complexity Citation:  Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu, "Built-in intermediate voltage testing for CMOS circuits," edtc, p. 372,  1995 European Design and Test Conference (ED&TC '95),  1995