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Euromicro Symposium on Digital Systems Design (DSD'03)   p. 408
A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits
Masanori Muroyama, Graduate School of Information Science and Electrical Engineering at Kyushu University
Akihiko Hyodo, Graduate School of Information Science and Electrical Engineering at Kyushu University
Takanori Okuma, Graduate School of Information Science and Electrical Engineering at Kyushu University
Hiroto Yasuura, Graduate School of Information Science and Electrical Engineering at Kyushu University

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231974
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Abstract
To transfer a small number, we inherently need the small number of bits. But all bit lines on a data bus change their status and redundant power is consumed. To reduce the redundant power consumption, we introduce a concept named active bits. In this paper, we propose a power reduction scheme for data buses using the active bits. Suppressing switching activity of inactive bits, we can reduce redundant power consumption. We propose various power reduction techniques using active bits and the implementation methods. Experimental results illustrate 20% - 35% on average and up to 54.2% switching activity reduction.
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Citation:  Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura, "A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits," dsd, p. 408,  Euromicro Symposium on Digital Systems Design (DSD'03),  2003