HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming

Euromicro Symposium on Digital Systems Design (DSD'03) p. 264
HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming
Karthikeyan Bhasyam, University of Minnesota
Kia Bazargan, University of Minnesota

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231945
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Abstract
We present an algorithm based on dynamic programming to perform the HW/SW partitioning and scheduling of a given task graph for minimum latency subject to resource constraint. The major contribution of this paper is to consider the edge communication delays in the dynamic programming solution of the problem. The algorithm has a polynomial run time complexity on trees. We also introduce a pruning technique to reduce the runtime of the worst-case scenario of directed acyclic graphs (DAGs). The algorithm has been implemented and the results are reported. A very fast quality heuristic is also proposed and implemented to provide good solutions in negligible run time.
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Citation: Karthikeyan Bhasyam, Kia Bazargan, "HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming," dsd, p. 264, Euromicro Symposium on Digital Systems Design (DSD'03), 2003

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