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Euromicro Symposium on Digital Systems Design (DSD'03)   p. 41
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors
Lin Li, Pennsylvania State University
N. Vijaykrishnan, Pennsylvania State University
Mahmut Kandemir, Pennsylvania State University
Mary Jane Irwin, Pennsylvania State University
Ismail Kadayif, Pennsylvania State University

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231898
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Abstract
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for building complex single processor based architectures, recent trends indicate a shift towards on-chip multiprocessor systems since they are simpler to implement and can provide better performance. An important problem in on-chip multiprocessors is energy consumption. In particular, on-chip cache structures can be major energy consumers. In this work, we study energy behavior of different cache architectures, and propose a new architecture, where processors share a single, banked cache using crossbar interconnects. Our detailed cycle-accurate simulations show that this cache architecture brings energy benefits ranging from 9% to 26% (over an architecture where each processor has a private cache).
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Citation:  Lin Li, N. Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin, Ismail Kadayif, "CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors," dsd, p. 41,  Euromicro Symposium on Digital Systems Design (DSD'03),  2003