Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems
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Abstract

This paper presents the architecture of a new memory Built-In Self-Repair approach targeting memories affected by high defect densities (several orders of magnitude higher than in current technologies). Such repair scheme is suitable for building memories in nano-technologies, which are subject to very high defect densities. The new approach allows combining two defected units to create a fault-free unit. For making this combination possible, the approach analyses the polarities of the errors produced by the faulty units of the memory, and combines units producing the same error polarities. The combination is done by means of functions that mask the errors of a particular polarity.
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