Abstract
Subtle failure mechanisms that arise from statistical distributions of the circuit parameters have been with us for many technology generations. However, since going from the 180 nm node to smaller nodes, the presence of these defects has increased to the point that they are no longer considered an occasional nuisance. They are a primary worry since they are difficult to design out with design rules, and they require special statistical and environmental settings to expose failure. This paper will describe the origins of parametric failures (PFs), present data showing the magnitude of their variance, and discuss the conditions under which we can expect failures to occur or to be detected during the test process. Detection is challenging, and PFs are a major source of field return. We expect PFs from intrinsic ICs (defect-free) and from extrinsic (defect) ICs. Resistive vias and metal cracks in general are a cause of PFs from ICs with parametric related defects. The detection of extrinsic PFs requires special care and a statistical analysis. This is a relatively new test paradigm [Seg03].