Quadruple Time Redundancy Adders

Whitney J. Townsend; Jacob A. Abraham; Earl E. Swartzlander, Jr.

doi:10.1109/DFTVS.2003.1250119

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems

Quadruple Time Redundancy Adders

Year: 2003, Pages: 250

DOI Bookmark: 10.1109/DFTVS.2003.1250119

Authors

Whitney J. Townsend, University of Texas at Austin
Jacob A. Abraham, University of Texas at Austin
Earl E. Swartzlander, Jr., University of Texas at Austin

Abstract

This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, Quadruple Time Redundancy, is compared with a non-redundant adder, a Tripple Modular Redundancy adder, and a Time Shared Triple Modular Redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with Time Shared Triple Modular Redundancy to which it is most closely related, Quadruple Time Redundancy results in a 40% - 55% reduction in hardware complexity while incurring a reasonable delay increase.

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Quadruple Time Redundancy Adders

Authors

Abstract

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