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Published Articles >> Table of Contents >> Abstract
Second IEEE International Workshop on Electronic Design, Test and Applications
p. 275
On Using Test Vector Differences for Reducing Test Pin Numbers
Marie-Lise Flottes, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Regis Poirier, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Bruno Rouzeyre, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10018
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| Abstract |
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We propose a method for reducing test data volume on System on Chip (SoC) architecture. This method reduces the required number of Automatic Test Equipment (ATE) output pins compared to the number of scan-in inputs on every core (horizontal compression). Compression and decompression are based on arithmetic operations and operators.
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 Additional Information
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Citation:
Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre,
"On Using Test Vector Differences for Reducing Test Pin Numbers,"
delta,
p. 275,
Second IEEE International Workshop on Electronic Design, Test and Applications,
2004
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