Abstract
Technology shrinkage has enabled the integration of multi million devices on silicon. This integration in digital and analog functionality is challenging since we now have to consider electrical effects that were not an issue with older process technologies. Communication systems, especially ICs targeted at SONET systems, have to Operate at very large data rates. Nowadays ICs with data rates greater that 3.125Giga Bits per Second (Gbps) are being designed. At these data rates, noise sources, coupling effects, and package parasitics need to be extremely well understood since these impact the design, test and characterization of devices. This paper will present a discussion on various sources of noise, provide an understanding for the package models, and how this can impact test and characterization.