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Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)   p. 20804
Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit
M.A. Abas, University of Newcastle Upon Tyne
G. Russell, University of Newcastle Upon Tyne
D.J. Kinniment, University of Newcastle Upon Tyne

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268980
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Abstract
The rapid pace of change in IC technology, specifically in speed of operation, demands sophisticated design solutions for IC testing methodologies. Moreover, the current technology of System-on-chip (SOC) makes great demands for testing internal speed accurately as the limitation on accessing internal nodes using I/O pins becomes more difficult. This paper presents two highresolution time measurement schemes for digital BIST applications, namely: Two-Delay Interpolation Method (TDIM) and Time Amplifier. The two schemes are combined to produce a completely new design for BIST time measurement which offers two main advantages: a low range of timing measurement which has never been achieved before, and a small size of layout occupying 0.2 mm2 or equivalent to 3020 transistors. These two features are undoubtedly compatible with present high-speed SOC design architectures.
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Citation:  M.A. Abas, G. Russell, D.J. Kinniment, "Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit," date, p. 20804,  Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04),  2004