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Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)   p. 20764
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Santiago Gonzalez Pestana, Philips Research Laboratories
Edwin Rijpkema, Philips Research Laboratories
Andrei Radulescu, Philips Research Laboratories
Kees Goossens, Philips Research Laboratories
Om Prakash Gangwal, Philips Research Laboratories

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268972
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Abstract
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency and throughput). In this paper we present a simulation-based approach to address this problem. We use XML to instantiate network components (routers, network interfaces) and their composition. NoCs are evaluated in terms of cost and performance by sweeping over different parameters (e.g. network topology, network interface queue depth). We then show, how we can obtain trade-off plots by using the results obtained with our simulation environment. Finally, by means of two examples we illustrate how trade-off plots can help the NoC designers in selecting the right network based on a set of different constraints.
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Citation:  Santiago Gonzalez Pestana, Edwin Rijpkema, Andrei Radulescu, Kees Goossens, Om Prakash Gangwal, "Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach," date, p. 20764,  Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04),  2004