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Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)   p. 10734
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268953
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Abstract
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to capture the processor description as well as the memory subsystem configuration, this environment offers support for system-level specification, intended for platform-based design. As a case study, it is presented the memory architecture exploration for a simple image processing application, yet a more robust environment evaluation is performed through the execution of some real-world benchmarks.
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Citation:  Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo, "Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology," date, p. 10734,  Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04),  2004

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