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Published Articles >> Table of Contents >> Abstract
Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)
p. 10318
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
Radoslaw Szymanek, Lund University
Francky Catthoor, IMEC and K.U.Leuven
Krzysztof Kuchcinski, Lund University
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268867
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| Abstract |
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This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. The input to our algorithm is an application given as an annotated task graph and a specification of a multi-layer memory architecture. The algorithm produces Pareto trade-off points representing different multi-objective execution options for the whole application. Different metrics are used to estimate parameters for application-level Pareto points obtained by merging all Pareto diagrams of the tasks composing the application. We estimate application execution time although the final scheduling is not yet known. The algorithm makes it possible to trade off the quality of the results and its runtime depending on the used metrics and the number of levels in the hierarchical composition of the tasks’ Pareto points. We have evaluated our algorithm on a medical image processing application and randomly generated task graphs. We have shown that our algorithm can explore huge design space and obtain (near) optimal results in terms of Pareto diagram quality.
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Citation:
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuchcinski,
"Time-Energy Design Space Exploration for Multi-Layer Memory Architectures,"
date,
p. 10318,
Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04),
2004
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