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Published Articles >> Table of Contents >> Abstract
Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)
p. 10148
Scheduling Reusable Instructions for Power Reduction
J. S. Hu, Pennsylvania State University
N. Vijaykrishnan, Pennsylvania State University
S. Kim, Pennsylvania State University
M. Kandemir, Pennsylvania State University
M. J. Irwin, Pennsylvania State University
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268841
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| Abstract |
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In this paper, we propose a new issue queue design that is capable of scheduling reusable instructions. Once the issue queue is reusing instructions, no instruction cache access is needed since the instructions are supplied by the issue queue itself. Furthermore, dynamic branch prediction and instruction decoding can also be avoided permitting the gating of the front-end stages of the pipeline (the stages before register renaming). Results using array-intensive codes show that up to 82% of the total execution cycles, the pipeline front-end can be gated, providing a power reduction of 72% in the instruction cache, 33% in the branch predictor, and 21% in the issue queue, respectively, at a small performance cost. Our analysis of compiler optimizations indicates that the power savings can be further improved by using optimized code.
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 Additional Information
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Citation:
J. S. Hu, N. Vijaykrishnan, S. Kim, M. Kandemir, M. J. Irwin,
"Scheduling Reusable Instructions for Power Reduction,"
date,
p. 10148,
Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04),
2004
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