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Published Articles >> Table of Contents >> Abstract
Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
p. 11174
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
Xi Chen, University of California at Riverside
Harry Hsieh, University of California at Riverside
Felice Balarin, Cadence Berkeley Laboratories
Yosinori Watanabe, Cadence Berkeley Laboratories
Full Article Text:
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10065
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| Abstract |
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System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulation will remain an important tool for making sure that implementations perform as they should. In this paper we present algorithms to automatically generate C++ checkers from any formula written in the formal quantitative constraint language, Logic Of Constraints (LOC). The executable can then be used to analyze the simulation traces for constraint violation and output debugging information. Different checkers can be generated for fast analysis under different memory limitations. LOC is particularly suitable for specification of system level quantitative constraints where relative coordination of instances of events, not lower level interaction, is of paramount concern. We illustrate the usefulness and efficiency of our automatic trace analysis methodology with case studies on large simulation traces from various system level designs.
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Citation:
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe,
"Automatic Generation of Simulation Monitors from Quantitative Constraint Formula,"
date,
p. 11174,
Design, Automation and Test in Europe Conference and Exhibition (DATE'03),
2003
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