Abstract
This paper proposes Selectively Clocked Logic (SCL) style b sed on skewed logic for noise-tolerant low-power high-performance applications.Variations of the logic style with multiple threshold voltage (MVth-SCL) and multiple oxide thickness (Mtox-SCL) techniques are also studied. Simulation results indicate that SCL, MVth-SCL, and Mtox-SCL circuits reduce the total power consumption (leakage plus switching power) of the ISCAS benchmark circuits by 51.5%, 53.1%, and 69.6%, respectively, with over 25% improvement in noise immunity compared to Domino circuits with comparable performance.