| Abstract |
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This paper presents a methodology for testing high-performance pipeline circuits with slow-spee testers. The technique uses a clock timing circuit to control data transfer in the pipeline in test mode. A clock timing circuit capable of achieving a timing resolution of 50ps in 0.18µm CMOS technology is presented. The design provides the ability to test the clock timing circuit itself.
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 Additional Information
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Index Terms- Delay-fault testing, high-performance testing, design for testability, design for delay testability
Citation:
Muhammad Nummer, Manoj Sachdev,
"DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers,"
date,
p. 10212,
Design, Automation and Test in Europe Conference and Exhibition (DATE'03),
2003
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